A data line in the lead region fabricated through a five-mask (5MASK) process in a conventional TFT-LCD manufacturing process is shown in the plan view of FIG. 1 and the sectional view of FIG. 2. The 5MASK process can include the following steps of: (1) forming a gate layer on a substrate 7 and etching the gate layer; (2) forming a gate insulating layer 3 (e.g., a SiNx layer) and an active layer and etching the active layer; (3) forming a source/drain metal layer (S/D layer) and etching the source/drain metal layer in the lead region to form a data line lead 2; (4) forming a passivation layer 1 (e.g., a PVX layer); and (5) forming a pixel electrode layer and then etching the pixel electrode layer to remove it from the lead region. The region B as shown in FIG. 1 is an electrostatic discharging region, and the region C is a pin region for connection with another device.
A data line in the lead region fabricated by a four-mask (4MASK) process is also represented with FIGS. 1 and 2. The 4MASK process can include the following steps of: (1) forming a gate layer on a substrate 7 and then etching the gate layer; (2) forming a gate insulating layer 3, an active layer, and a source/drain metal layer, etching the source/drain metal layer in the lead region to form a data line lead 2; (3) forming a passivation layer 1; and (4) forming a pixel electrode layer and then etched the pixel layer to remove it from the lead region.
The two processes both provide a lead region structure that includes an insulating upper layer and an insulating bottom layer with a conductive wire therebetween. Particles on the substrate before and during deposition of the source/drain metal layer, electrostatic breakdown in the lead region, and breakage of the data line lead due to press in a subsequent process may all render the data line lead open, resulting in a bright line in a final product and degrading the quality of the product.